The entire project work

Undertaking Simulation Results

The full undertaking work has been tested with Multisim simulation package ( from National Instruments ) every bit good as Proteus simulation package ( from Labcenter Electronics ) . We are showing the undertaking simulation consequences from Proteus simulation package. Initially, we are giving single blocks of the undertaking and eventually we are giving the complete undertaking in both unfastened cringle and closed cringle conditions.

Power Amplifier Block

The undermentioned circuit is an execution of power amplifier block of the undertaking:

The circuit has been tested for an input sine wave with a peak electromotive force of +100mV. The frequence of the sine moving ridge is 250Hz. The wave forms for input and end product sine moving ridges can be observed from the CRO. The first wave form represents the input electromotive force Vin to the power amplifier. The 2nd wave form represents the end product electromotive force Vout from the power amplifier. The wave forms in the CRO are corroborating that the addition A of the power amplifier is 50. ( Observe channel scenes of the CRO )

The circuit has been tested for two input sine moving ridges with peak electromotive forces +50mV and +100mV severally. The frequence of each sine moving ridge is 250Hz. The wave forms for these sine moving ridges can be observed from the CRO. The first and 2nd wave forms will stand for the input electromotive forces V1 and V2 to the differential amplifier. The 3rd wave form represents the end product electromotive force Vout from the differential amplifier. The wave forms in the CRO are corroborating that the end product electromotive force Vout is the difference between the input electromotive forces V2 and V1. ( Observe channel scenes of the CRO )

The above circuit implements the digital hold strategy utilizing a microcontroller. The input electromotive force Vin is fed into the ADC bit. The ADC bit converts this parallel input to a corresponding digital end product. The microcontroller takes this digital value and shops in a waiting line. Like this the procedure will be repeated for a specific figure of samples. After taking the needed figure of sample digital values the microcontroller starts directing each sample one by one in FIFO order to its DAC circuit. During the bringing of each sample the microcontroller takes a fresh sample from ADC and shops it in a waiting line. The DAC circuit converts the digital value to analog end product. This parallel end product electromotive force ( indicated as Vout in circuit diagram ) is the delayed parallel input electromotive force.

The circuit implements the clip hold utilizing a information construction called “ Queue ” . The size of the waiting line decides the sum of the clip hold ( Of class, the clip hold besides depends on the ADC transition clip ) . We are taking the size of the waiting line as the figure of samples. We can alter the figure of samples by pressing the switches that are connected to the microcontroller. The generated clip hold can be calculated about from the figure of samples. Therefore by altering the figure of samples we can increase/decrease the clip hold.

The circuit uses an external ADC0804 IC ( from National Semiconductor ) for analog-to-digital transition. The ADC0804 IC has an internal clock generator. To utilize the internal clock generator of the ADC0804 the CLK IN and CLK R pins are connected to a capacitance and a resistance. Typical values are R = 10K? and C = 150pF. In this instance, the transition clip of the ADC is 110µs. In topographic point of ADC0804, we can utilize any other ADC bit that has 8 or more spots of declaration. The higher-resolution ADC provides a smaller measure size, where measure size is the smallest alteration that can be discerned by an ADC.

The circuit uses registries to implement digital-to-analog transition. In topographic point of these registries, we can utilize any digital-to-analog convertor IC such as DAC0808 IC ( from National Semiconductor ) .

The circuit has been tested with Proteus simulation package tool and we got the undermentioned consequences on the CRO:

The circuit has been tested for an input sine wave with a peak electromotive force of +5V. The frequence of the sine moving ridge is 250Hz. The wave forms for input and end product sine moving ridges can be observed from the CRO. The first wave form represents the input electromotive force Vin to the ADC bit. The 2nd wave form represents the end product electromotive force Vout from the microcontroller ‘s DAC circuit. The wave forms in the CRO are corroborating that the end product electromotive force is a delayed version of the input electromotive force. Note that the 2nd wave form in the CRO is the inversion of the first wave form. Of class, this happens merely for specific hold clip. If we change the hold clip so we may non acquire the exact upside-down end product sine moving ridge for the input sine moving ridge. ( Observe channel scenes of the CRO )

Summarizing Amplifier Block

The undermentioned circuit is an execution of a summing amplifier block of the undertaking:

In the above circuit we have R1 = R2 = R3 = 10K? . Hence, the end product electromotive force Vout = – ( V1 + V2 ) . Note that this end product electromotive force is a negative electromotive force ( if input electromotive forces are positive ) . So, this negative end product electromotive force is fed into an inverting amplifier ( indicated as U2 in circuit diagram, which is an inverting amplifier ) that outputs the positive end product electromotive force. For illustration, if V1 is +100mV and V2 is +100mV so the end product electromotive force Vout is +200mV.

The circuit has been tested with Proteus simulation package tool and we got the undermentioned consequences on the CRO:

The circuit has been tested for two input sine moving ridges with peak electromotive forces +100mV and +100mV severally. The frequence of each sine moving ridge is 250Hz. The wave forms for these sine moving ridges can be observed from the CRO. The first and 2nd wave forms will stand for the input electromotive forces V1 and V2 to the summing amplifier. The 3rd wave form represents the end product electromotive force Vout from the summing amplifier. The wave forms in the CRO are corroborating that the end product electromotive force Vout is the summing up of the input electromotive forces V1 and V2. ( Observe channel scenes of the CRO )

Complete Project Circuit ( Open Loop Condition )

The undermentioned circuit is an execution of complete undertaking in unfastened loop status:

In the above circuit “ INPUT SIGNAL ” is a sine moving ridge with a peak electromotive force of +100mV. The frequence of the sine moving ridge is 250Hz. At first, this input signal is fed into a Power Amplifier. The addition of the Power Amplifier is taken as 50. The power amplifier gives an end product signal, which is a sine moving ridge with +5V extremum. In simulation, we wo n’t acquire any deformation with Power Amplifier ‘s end product signal. But, in world every Power Amplifier creates some deformation. So, we are making some deformation utilizing resistance and rectifying tubes explicitly. This deformed signal is fed into a differential amplifier ( other input of the differential amplifier is land ) .

The end product signal of the differential amplifier is delayed for a specific period of clip utilizing a digital-delay strategy. The digital hold strategy is implemented with the aid of a microcontroller. The user can set the hold by pressing switches that are connected to the microcontroller. Now, the original signal and delayed signals are sent to a summing amplifier. The end product signal of the summing amplifier is the second harmonic constituent ( Indicated as “ OUTPUT SIGNAL ” in circuit diagram ) . If we send this 2nd harmonic constituent as other input ( in topographic point of land signal ) to the differential amplifier so the harmonic deformation will be reduced. This is explained in the following circuit.

The circuit has been tested with Proteus simulation package tool and we got the undermentioned consequences on the CRO:

We can detect 4 moving ridge signifiers from the above CRO. The first moving ridge signifier is the end product signal from the Power Amplifier, which is a sine moving ridge with a extremum of +5V and its frequence is 250Hz. The 2nd moving ridge signifier is a deformed signal. As already discussed, the deformation is created by registry and rectifying tubes in the circuit. The 3rd wave signifier is the delayed signal. Note that the delayed signal is an inversion of deformed signal. Of class, this happens merely for specific sum of hold clip. The 4th signal is the second harmonic constituent signal. ( Observe channel scenes of the CRO )

In the above circuit “ INPUT SIGNAL ” is a sine moving ridge with a extremum of +100mV. The frequence of the sine moving ridge is 250Hz. The circuit is same as the old one but we are deducting 2nd harmonic component signal from Power Amplifier ‘s signal. This reduces the harmonic deformation.

The circuit has been tested with Proteus simulation package tool and we got the undermentioned consequences on the CRO:

We can detect 4 moving ridge signifiers from the above CRO. The first moving ridge signifier is the end product signal of the power amplifier. The 2nd moving ridge signifier is the deformed signal. We can detect the decrease of harmonic deformation from the 2nd moving ridge signifier. The 3rd wave signifier is the delayed signal, which is an inversion of deformed signal. Finally, the 4th moving ridge signifier is the second harmonic constituent signal. Note that the amplitude of the harmonic constituent has been reduced due to the negative feedback. ( Observe channel scenes of the CRO )