Emergency locator transmitter VLSI Approach

This paper deals with the VLSI Approach for design of Emergency Locator Transmitter of Aircraft with Global Positioning System ( GPS ) Receiver. Emergency Locator Transmitter ( ELT ) is an exigency equipment fitted in the air trade which will turn up the place during the event of a clang.

The COSPAS-SARSAT ( C/S ) orbiter system has been supplying exigency alarming from system compatible ELT for a figure of old ages and therefore, has been instrumental in salvaging many lives around the universe. However, turn uping the site of the clang utilizing this orbiter system is less accurate, equivocal and sometimes involves unnatural hold. But, now a yearss, engineerings such as the Global Positioning System ( GPS ) can supply good location truth.

The integrating of a GPS receiving system in the bing ELT and re planing the ELT utilizing VLSI engineering, would unite really accurate location finding and near instantaneous hurt qui vive. These sweetenings would cut down the overall clip required to finish the deliverance operation. The VLSI design of this integrated unit will be compact, efficient and more dependable.

The primary aim of this paper is to depict the rules, VLSI design and analysis of an integrated GPS receiving system and the ELT so that the GPS receiving system could supply location information to be incorporated in the familial message of ELT. This new equipment ELTGPS could be incorporated with a batch of added excess characteristics so the equipment can be used for non exigency operations besides.

The proposed VLSI attack for ELT based GPS design is done sing low power with local supply which turns on during air trade clang, high truth, low Si country, integrating of all blocks in individual dice. The following are the bomber blocks used in the proposed GPS based ELT system and their integrating with simulation consequences are described below.

  1. Power Supply and electromotive force regulator
  2. Reference circuit
  3. Double Port SRAM
  4. GPS Receiver
  5. G-Switch
  6. Timer & A ; Counter
  7. Modulator
  8. Crystal Oscillator
  9. Phase Lock Loop
  10. Digital to Analog Converter
  11. Power Amplifier
  12. Buzzer Driver
  13. Manual Reset
  14. Integration

1 ) Power Supply and electromotive force regulator:

Two 5V batteries are used in the proposed design, one 5V battery with regulated power supply of 2.5V is for double port RAM and GPS and other 5V battery with regulated power supply of 2.5V for all the other blocks like crystal, PLL, DAC, modulator, mention circuit, timer, MUX, power amplifier e.t.c. Double port RAM and GPS 5V battery will be continuously charged through internal air trade power supply because GPS should continuously track latitude / longitude place and shop the informations in double port RAM. Power supply for all the blocks used in assorted signal bit will be provided by other 5V battery which will turn on during aircraft clang through G switch. Two Internal regulators which converter 5V to 2.5V supply used for powering all the blocks for better truth. Figure 1 illustrates the Block diagram of Linear Voltage Regulator Circuit [ 1 ] . The basic edifice blocks for additive electromotive force regulator are operational Tran conductance amplifier ( OTA ) , feedback elements ( Resistors ) and pass transistor to beginning current from supply.

The followers are the specifications for the Voltage Regulators

  • Settling Time & lt ; 5us
  • Load Regulation & lt ; ±25mV
  • Line Regulation & lt ; ±10mV

2 ) Mention Circuit:

In assorted signals french friess mention circuit helps in supplying changeless mention electromotive force irrespective of procedure, electromotive force and temperature fluctuations. The most popular architecture is bandgap [ 2 ] mention circuit bring forthing low temperature coefficient changeless end product electromotive force. The bandgap rule is adding a negative temperature coefficient with scalar generation of positive temperature coefficient to bring forth temperature independent end product electromotive force. A rectifying tube connected bipolar transistor ( VBE ) electromotive force is -ve temperature coefficient naturals with k*?VBE provides +ve temperature coefficient to bring forth 1.23V changeless end product mention electromotive force used by electromotive force regulators, PLL, DAC and power amplifier. Figure 2 illustrates block diagram of Bandgap Reference circuit.

The base-emitter electromotive force of a BJT is given in below equation which is complementary to absolute temperature.

If two BJTs operate with different emitter current densenesss ( by a ratio of N ) , so the difference between their base-emitter electromotive forces is given in below equation which is relative to absolute temperature.

By taking the amount of VBE + ?VBE we get changeless end product electromotive force of 1.23 which is about equal to energy bandgap of Si in peculiar engineering.

The followers are the specifications for the Bandgap mention circuit

  • Settling Time & lt ; 1us
  • Temperature Sensitivity & lt ; 20ppm/°C
  • Low Quiescent Current

3 ) Dual Port SRAM:

In GPS based ELT system a double port RAM circuit [ 3 ] is used to continuously hive away the latitude and longitude locations in normal manner and supply the last updated information to transmitter through DAC, Modulator and power amplifier during aircraft clang. Double port SRAM is R/W memory circuit that permits the alteration ( composing ) of information spots to be stored in a memory array, every bit good as their retrieval ( reading ) . The SRAM design consists of SRAM cells, pre-charge, sense amplifiers, MUX, NAND gates, AND gates, NOR Gatess and row decipherer. The popular, full CMOS 6-transistor cell constellation was used to plan the SRAM memory array. The full CMOS constellation is shown in figure 3. Some of the advantages of utilizing full CMOS SRAM constellation are low inactive power dissipation, superior noise borders, high shift velocities and suitableness for high-density SRAM arrays.

Inactive RAM Cell:

The full CMOS 6-transistor cell constellation was chosen for the cell array. Figure 2 shows the schematic of the 6-T cell. The 6-T cell consists of two cross coupled inverters connected with the two nmos transistors on both the terminals. Each nmos transistor is connected to an inverter on one side and spot line on the other side. The information value is stored in the net connected to the left side of the M4 nmos in figure 2. The opposite informations value is stored in the net connected to the right side of the M3 nmos. The input signal i.e. , address line comes from the row decipherer, allows the cell to be connected to the complementary spot lines during reading and authorship and gulfs otherwise.

Sensor Amplifier Circuit:

A sense amplifier circuit is used to read the informations from the cell. In add-on, it helps cut down the hold times and minimizes power ingestion in the overall SRAM by feeling a little difference in electromotive force on the spot lines ( 2 ) . A low-tension sense amplifier was used in the SRAM design to back up high public presentation. 8 sense amplifier circuits were used for the SRAM design, one for each column.

Decoder Circuit:

A row decipherer is used to decrypt the given input reference and choose the wordline. When executing a write or, read operation merely one of the row is selected and 8 spots of informations is transmitted. There are 8 rows and row contained 8 cells each. The row decipherer selects one of those rows, depending on the 3 spot address given to it. In order to plan an 8X8 SRAM a 3×8 decipherer is used. Number of wordline peers to the figure of rows in the SRAM cell array. The decipherer selects 1 of 8 wordlines, with regard to the input reference. The end product of the decipherer is fed to a 2-input AND. This AND is the wordline driver. This AND supports a big electrical capacity on the wordline. Each cell loads the wordline with two transistors. Therefore, in the design there would be 16 transistors per wordline organizing a big electrical capacity on the wordline. Other input to this AND is the Clock. Merely when both Clock and decipherer end product signals are enabled, the AND enables a wordline to the rows of SRAM cell arrays. In a typical SRAM design, the end product from the decipherer would straight enable the wordline. This AND was introduced in the design to accomplish a clock enabled design. A NAND based decipherer is used in the design. NAND based design is suited as it faster. In both read and write manner clocking information is illustrated in figure 4 and figure 5.

The followers are the specifications for the Dual port SRAM

  • Low Power
  • Interrupt Function
  • Parallel Interface
  • 1024K Density
  • 10ns Speed
  • Bus Width: 8-16
  • Temperature -40 to 125° C
  • LVTTL I/O Level

4 ) Global Positioning System Receiver:

In GPS based ELT system Global Positioning System Receiver [ 4 ] is used to uninterrupted update the latitude and longitude informations of the air trade into double port RAM. The input signal to the GPS receiving system is linear which is converted to parallel digital informations and shops in double port RAM. The block diagram of GPS receiving system is illustrated in figure 6, in this application the Global Positioning System ( GPS ) Receiver is a 10 channel receiving system system which is decided based upon bandwidth. It features fast-acquisition hardware, integrated RF filtering, ADC, TCXO, reset circuits, real-time clock with on-board crystal, and an integrated LNA that allows operation with either active or inactive aerials. The user needs merely supply DC power and a GPS signal. The 10-channel receiving system allows all orbiters in position to be tracked, supplying an over-determined solution to minimise place leaps caused by single orbiter obstruction. The fast-acquisition hardware design greatly reduces the clip for signal acquisition when the receiving system is ab initio powered up. The GPS receiving system system operates from a individual battery supply 2.5 VDC for low power ingestion.

The GPS receiving system is designed for high-performance and low power ingestion, with the benefit of utilizing the system ‘s bing clock mention. This receiving system is ideal for integrating into ELT system. The lone external constituents required are the GPS RF filter, an IF filter ( typically designed from cheap discrete ) , a three-component PLL cringle filter, and a few other resistances and capacitances. The designed GPS receiving system system integrates the mention oscillator nucleus, the VCO and its armored combat vehicle, the synthesist, a 1- to 3-bit ADC, and all signal way blocks except for the 1st IF filter.

The followers are the specifications for the Global Position System Receiver

  • Acquisition Time & lt ; 1 Second
  • Tracking & lt ; 2.5meters
  • Temperature -20 to 85° C
  • Altitude -1000 pess to 60,000 pess
  • Signal Degree: -160dBm to -125dBm
  • Frequency: 1575.42 MHz
  • Noise Figure: 1.5 dubnium
  • Electric resistance: 50 ohms

5 ) G Switch:

G Switch is sensor component activates ELT system with a alteration of speed of 3.5 Federal Protective Services ± 0.5fps both under normal conditions and while being subjected to 30 G ‘s of cross axis forces. The ELT 110-406HM has an extra five G-switches supplying for six activation coverage. The extra five G-switches activate at a G force of 12 G ‘s. The G switch is designed with MOSFET driving a battery ( i.e. , battery bends on ) during aircraft clang which is detected by the speed of aircraft. Rx Antenna

The followers are the specifications for the G-Switch

  • Fast Recovery clip.
  • Low ON opposition.

6 ) Timer and Counter:

The timer and counter [ 3 ] are indispensable blocks in ELT design because when The ELT activates automatically during a clang and transmits the criterion swept tone on 121.5 MHz and 243.0 MHz. The 406.025 MHz sender turns on every 50 seconds for the continuance of 440 msecs ( for conveying standard short message ) or 520 msecs ( for conveying optional long message ) . During this clip, an encoded digital message is sent to the orbiter. The information contained in this message is consecutive figure of the sender, state codification, place carbon monoxide ordinates etc. The 406.025 MHz sender will run for 24 hours and so close down automatically. The 121.5/243.0 MHz sender will go on to run till the battery unit has exhausted its power which typically will be at least 48 hours.

7 ) Modulator:

In GPS based ELT system a frequence modulator is required to modulate the parallel informations provided from DAC which is at low frequence to 406MHz or 121.5MHz/243 informations by utilizing bearer signal. Frequency transition uses the information signal from DAC, Vm ( T ) to change the bearer frequence within some little scope about its original value. Here are the three signals in mathematical signifier:

  • Information: Vm ( T )
  • Carrier: Vc ( T ) = Vco wickedness ( 2?fc T + Ô )
  • Frequency modulation: VFM ( T ) = Vco wickedness ( 2? [ fc + ( ?f/Vmo ) Vm ( T ) ] ?t + ? Ô )

We have replaced the bearer frequence term, with a time-varying frequence. We have besides introduced a new term: ?f, the peak frequence divergence. In this signifier, you should be able to see that the bearer frequency term: fc + ( ?f /Vmo ) Vm ( T ) now varies between the extremes of fc-?f and fc+?f. The reading of ?f becomes clear: it is the farthest off from the original frequence that the FM signal can be. Sometimes it is referred to as the “ swing ” in the frequence.

We can besides specify a transition index for FM, correspondent to Be:

? = ?f/fm, where frequency modulation is the maximal modulating frequence used.

The simplest reading of the transition index, ? ?is as a step of the peak frequence divergence, ?f. In other words, ? represents a manner to show the peak divergence frequence as a multiple of the maximal modulating frequence, frequency modulation, i.e. ?f = ?fm.

The followers are the public presentation specifications for the Frequency Modulator


As we have already shown, the bandwidth of a FM signal may be predicted utilizing:

BW = 2 ( ? + 1 ) frequency modulation ; where ? is the transition index and frequency modulation is the maximal modulating frequence used.

FM wireless has a significantly larger bandwidth than AM wireless, but the FM wireless set is besides larger. The combination keeps the figure of available channels about the same. The bandwidth of an FM signal has a more complicated dependence than in the AM instance. In FM, both the transition index and the modulating frequence affect the bandwidth. As the information is made stronger, the bandwidth besides grows.


The efficiency of a signal is the power in the side-bands as a fraction of the sum. In FM signals, because of the considerable side-bands produced, the efficiency is by and large high. The side-band construction is reasonably complicated, but it is safe to state that the efficiency is by and large improved by doing the transition index larger. But if you make the transition index larger, so do the bandwidth larger which has its disadvantages. As is typical in technology, a via media between efficiency and public presentation is struck. The transition index is usually limited to a value between 1 and 5, depending on the application.


FM systems are far better at rejecting noise than AM systems. Noise by and large is dispersed uniformly across the spectrum. The amplitude of the noise varies indiscriminately at these frequences. The alteration in amplitude can really modulate the signal and be picked up in the AM system. As a consequence, AM systems are really sensitive to random noise. An illustration might be ignition system noise in your auto. Particular filters need to be installed to maintain the intervention out of your auto wireless. FM systems are inherently immune to random noise. In order for the noise to interfere, it would hold to modulate the frequence someway. But the noise is distributed uniformly in frequence and varies largely in amplitude. As a consequence, there is virtually no intervention picked up in the FM receiving system. FM is sometimes called “ inactive free, “ mentioning to its superior unsusceptibility to random noise.

8 ) Crystal Oscillator:

On bit crystal oscillator are most popular to bring forth clock upto 10MHz-20MHz frequence with less than 2 % truth. The crystal oscillator [ 5 ] provides input frequence to phase lock cringle and obtain 121.5 MHz / 243 MHz / 406 MHz end product frequences. A crystal oscillator is developed by utilizing a piezoelectric stuff ; one which transforms electrical energy to mechanical energy and frailty versa. The transmutation occurs at the resonating frequence of the crystal. This happens when the applied AC electric field is sympathetic in frequence with the mechanical resonance of the piece of crystal. Since this characteristic can be made really accurate, crystals are usually used where frequence stableness is critical. Typical frequence tolerance is.005 to 0.3 % . The advantage of a crystal oscillator in this application is its broad scope of positive reactance values over a narrow scope of frequences. However, there are several scopes of frequences where the reactance is positive ; these are the cardinal, and the 3rd and 5th mechanical overtones. Since the coveted frequence scope in this application is ever the cardinal, the overtones must be suppressed. This is done by cut downing the cringle addition at these frequences. Normally, the amplifier ‘s addition axial rotation off, in combination with the crystal parasitic and load capacitances, is sufficient to cut down addition and prevent oscillation at the overtone frequences. The block diagram of the crystal oscillator is illustrated in figure 8 which consists of amplifier, Crystal, feedback resistances and capacitances.

The followers are the specifications for the Crystal Oscillator

  • Frequency Scope: 10MHz – 20MHz
  • Addition: 20V/V
  • Output slew rate: 2V/ns

9 ) Phase Lock Loop:

Phase lock cringle circuit [ 6 ] operates as frequence synthesist in this application by taking input signal of 20MHz from crystal oscillator and supplying end product frequences 121.5MHz / 243MHz / 406MHz. The block diagram of the stage lock cringle in illustrated below Figure 9.

A phase-locked cringle is a feedback system that operates on the extra stage of nominally periodic signals. This is in contrast to familiar feedback circuits where electromotive force and current amplitudes and their rate of alteration are of involvement. The major blocks in stage lock cringle are phase frequence sensor, charge pump, cringle filter, electromotive force controlled oscillator and splitter.

The phase-detector compares the frequence and stage of the mention frequence signal, against the stage of the VCO end product signal [ Feedback Frequency ] . Output of the phase-detector is a voltage proportional to the stage difference between its two inputs. The cringle is considered “locked” if the stage difference is changeless with clip. The stage sensor end product is digital which is converted to analog electromotive force by utilizing charge pump circuit, the end product of the charge pump circuit filtered by the loop-filter. Loop-filter is a lowpass filter, which suppresses the high frequence signal constituents and noise. Output of the loop-filter is applied to the VCO as the control electromotive force. This control electromotive force changes the frequence of the VCO in a way that reduces the stage difference between the input signal and the local oscillator. When the cringle is locked, the control electromotive force is such that the frequence of the VCO is precisely equal to the mean frequence of the input signal ; nevertheless, there may be a inactive stage mistake nowadays. This mistake tends to be little in a well-designed cringle. In GPS based ELT system an input of 20MHz is used by PLL from crystal oscillator to bring forth end product frequences of 406MHz, 243MHz and 121.5MHz, this frequence redstem storksbills are used by modulator to modulate the informations w.r.t clock signal.

The followers are the specifications for the Phase Lock Loop

  • Phase Noise: -75dBc
  • Loop Bandwidth: 0.5MHz
  • Phase Margin: 60 deg
  • Settling Time: 50us
  • Muffling Factor: 1.1
  • Jitter Mean: ±75 PS

10 ) Digital to Analog Converter:

A current guidance Digital to Analog Converter [ 6 ] is used in this application which will converter SRAM digital informations to analog value and transmit through modulator and power amplifier. The current-steering DAC architecture is illustrated in figure 10. There is a figure of current beginnings and switches. Depending on the input codification, the current from the corresponding beginnings is directed by the switches to the end product and terminated by an resistance. The duplicate mistakes will strongly act upon the public presentation.

Alternatively of utilizing a current beginning with the nominal value one uses unit current beginnings in analogue. We will so hold the same type of border duplicate mistakes for each component. Second, we may besides utilize particular layout techniques, such as interdigitized or common-centroid in order to smooth out the influence of ranked mismatch mistakes.

The followers are the specifications for the Digital to Analog Converter

  • Differential Non-Linearity & lt ; ±0.5LSB
  • Integral Non-Linearity & lt ; ±1LSB
  • Settling Time & lt ; 6ns
  • Signal to resound ratio: 56dB.
  • Gain Error, Offset Error & lt ; 3 LSB

11 ) Power Amplifier:

In RF transceivers power amplifiers plays major function which will take a small-amplitude signal at the end product RF frequence as its input and drives a high power representation of the input into a low electric resistance burden. In GPS based ELT system the parallel end product of the modulator is non capable to drive the aerial and hence power amplifier circuit is used to hike the power degree of the signal, because the peak power degrees required will be significantly higher than the modulator can provide on its ain. The power amplifier is one of the concluding blocks to be implemented and integrated with the other blocks onto a individual CMOS bit. One of the cardinal grounds for the general industry-wide reluctance to travel the execution of the power amplifier to CMOS is the fact that while the power amplifier is on, it can rule the power ingestion of the full transceiver. The power amplifier end product power degree is on the order of 100s of factory Wattss or more, the power that the power amplifier demands to present to its burden in itself is a big per centum of the entire power consumed by the full sender. In kernel, the power amplifier converts the DC power from the battery into RF power delivered to the burden. Unless that power transition is lossless, which is possible merely as an ideal abstraction, the power amplifier itself will devour power, over and above what it delivers. The of import specification of the power amplifier is efficiency and a category C power amplifier is used in this application because it provides more than 90 % efficiency.

The followers are the specifications for the Power Amplifier circuit

  • Operating frequence 406MHz upper limit
  • Over 32dB Power Gain
  • 15dB Output Power Control Range
  • Second Harmonic -26dBc
  • Third Harmonic -40 dBc

12 ) Buzzer Driver:

A Buzzer driver is used to blow the horn end product during aircraft clang. When an air trade is crashed so G-switch will turn on which activate GPS based ELT system and parallel thrusts buzzer to blow horn or it can besides drive an LED system.

13 ) Manual Reset:

A Manual reset option is provided for GPS based ELT system along with G-switch to prove the application on board along with making an environment of aircraft system.

14 ) Integration:


One of the primary characteristics of the ELT 110-406 is its simpleness of operation. Equally long as ELT is located into its climb tray, it will trip in clang, neither the cockpit exchange nor the ELT unit switch can be positioned to forestall automatic activation once the unit is mounted decently. ELT is besides designed against human mistake and abuse in respects to automatic activation. The unit activates merely when firmly mounted in its tray [ G-Switch ON ] . The ELT can non be accidently activated by droping, unsmooth handling or during transportation.

When the ELT is activated, the presence of the exigency swept tone and a flashing panel visible radiation indicates a usually functioning unit. The front panel visible radiation must instantly get down to continuously brassy upon ELT activation. Under normal operation the switch constellation on your front panel is the down place, reading “ARM” . The switch on the ELT unit will besides be positioned down to read “OFF” . Should an exigency arise to the grade that manual wants to trip ELT, contrary either switch so it is in the up ( “ON” ) place. Remember, that every bit long as the front panel and ELT switches are in the ARM/OFF place the ELT will automatically trip on impact. If ELT is activated by chance so we need to reset it, which can be done by traveling front panel switch to “ON” so instantly swaying it back to “ARM” . We can besides reset the ELT at the unit itself by positioning the switch on the ELT up to “ON” so instantly back down to “OFF” .


Figure 12 illustrates the integrating of all above blocks to find the functionality for GPS based ELT system. The functionality of the GPS based ELT system is described as follows, GPS based ELT system has two manners

  1. Normal manner [ Aircraft is all right ]
  2. Aircraft clang manner

( a ) Normal Mode: In normal operation aircraft is running all right and the planetary place system having aerial will continuously track the latitude and longitude locations at a velocity of 1575MHz and shops the informations in double port RAM. In normal operation bandgap mention circuit ( 1 ) will bring forth 1.23V mention electromotive force to voltage regulator and electromotive force regulator will bring forth 2.5V end product w.r.t 5V input from battery for low power operation. The electromotive force regulator 2.5V end product powers planetary place system receiving system and double port RAM.

( B ) Aircraft clang manner: When air trade is crashed i.e. , aircraft clang manner so G-Switch will turn on the bandgap mention circuit ( 2 ) and electromotive force regulator ( 2 ) which will power up all the other blocks [ Crystal oscillator, PLL, modulators, digital to analog convertor, timer, counter and power amplifier ] parallely A Buzzer driver is used to blow the horn or it can besides drive an LED system. Initially crystal oscillator will get down working one time voltage regulator ( 2 ) provides power and crystal oscillator will supply 15MHz low jitter clock to PLL. PLL will bring forth lock signal when the desired end product frequences 406MHz, 121.5MHz/243MHz clocks/carrier signals are obtained for modulators and digital to analog convertor, the lock signal activates the read manner of double port RAM which will latch the informations on to the digital to analog convertor. GPS based ELT system in aircraft clang manner will convey 121.5MHz/243MHz clock signals continuously and 406.025 MHz informations sender turns on every 50 seconds for the continuance of 440 msecs ( for conveying standard short message ) or 520 msecs ( for conveying optional long message ) . During this clip, an encoded digital message is sent to the orbiter. The information contained in this message is consecutive figure of the sender, state codification, place carbon monoxide ordinates etc. The digital to analog convertor end product to given to modulator, after transition [ informations and bearer signal ] the information is given to power amplifier to hike end product power degree and thrust transmission aerial.

GPS based ELT system has standard codification format of transmittal and there are three coding options of this protocol that can be used with ELTs. An synergistic diagram of each, picturing the information which should be coded into the beacon is provided below.